1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically, it relates to a multilayer semiconductor device including a plurality of semiconductor chips.
2. Description of the Related Art
Recent electronic equipment needs to be high-performance, small, and lightweight. Therefore, semiconductor devices used for electronic equipment also need to be high-performance and small. In addition to the large-scale integration of semiconductor devices, downsizing of packages has progressed. For example, BGA (Ball Grid Array) and CSP (Chip Size Package) have been developed.
In conventional electronic equipment, as shown in FIG. 1, semiconductor devices 14 and 15, such as a CPU, a controller, a memory, or the like, are mounted on a printed board 16 and connected to each other with wirings on the printed board 16. When the semiconductor devices are arranged two-dimensionally as shown in FIG. 1, the area of the printed board needs to be large.
Recent digital information appliances need to be smaller and more lightweight, and have higher performance. In order to meet these requirements, various techniques for layering a plurality of semiconductor chips have been developed.
FIG. 2 shows a multilayer semiconductor device in which two kinds of semiconductor chips 1 and 2 are layered. When a plurality of chips are layered, the chips have two types of pads 5, that is, a pad having a circuit terminal of the multilayer semiconductor device, and a pad for connecting the chips to each other having no circuit terminal of the multilayer semiconductor device. That is, the latter pad is only used for data communication between the chips, and information is not output from the pad to the outside.
When the semiconductor devices 14 and 15 are mounted on the printed board 16 and connected to each other as shown in FIG. 1, the semiconductor devices 14 and 15 can be tested individually because they have individual terminals.
However, when a plurality of chips are layered on a printed board 7 and encapsulated in a package as shown in FIG. 2, a chip having no circuit terminal of the multilayer semiconductor device cannot be tested individually.
In order to test the layered chips individually, it is necessary to provide a test stub line 8 for connecting the pad having no terminal of the multilayer semiconductor device to a test signal pin 13 as shown in FIG. 2. Through the added test signal pin 13, the layered chips can be tested individually.
However, the test stub line 8 shown in FIG. 2 is used only during a test and is useless during the normal operation. During the normal operation in which signals are transmitted between the semiconductor chips 1 and 2, the test stub line 8 creates a new problem where ringing due to reflection distorts the signal waveform.
FIGS. 3A and 3B show simulation waveforms showing the influence of the test stub line. The simulation waveforms are waveforms in a main signal pad 12 (FIG. 2) when a random pattern is generated. FIG. 3A shows the case where the stub line is short. FIG. 3B shows the case where the stub line is long. As is clear from the simulation results, when the stub line is long, the signal quality is deteriorated. The higher the data speed of the device, the more serious the deterioration of the signal quality.
In addition, although the test stub line 8 shown in FIG. 2 is used only during a test and is useless during the normal operation, the test stub line 8 and the signal line are connected in one-to-one correspondence. This causes the number of pins of the multilayer semiconductor device to be larger. Consequently, the area of the multilayer semiconductor device increases, or the numbers of power source pins and ground pins allocated to the multilayer semiconductor device are reduced.
The following documents discuss the testing of layered chips.
Japanese Unexamined Patent Publication No. 2002-217367 discusses providing test terminals on the outer side of terminals of a semiconductor device. When the semiconductor device is in a wafer, tests are carried out through the test terminals. After the tests are completed, the test terminals are cut off.
Japanese Unexamined Patent Publication No. Tokkai Hei 11-274395 discusses a semiconductor device having a separating circuit. The separating circuit can switch between connection and disconnection between the inner circuit and pads of chips connected to a common terminal of the semiconductor device.
As described above, a multilayer semiconductor device in which a plurality of semiconductor chips are layered has pads of semiconductor chips that are not connected to any external terminals, and therefore the semiconductor chips cannot be tested individually.
In addition, in the case where a test stub line and a test signal pin are provided in order to test the semiconductor chips individually, the test stub line, which is not used during the normal operation, causes reflection and crosstalk and deteriorates the signal quality in the normal operation.